Basic Study on Learning Capabilities and Massively Parallel Processing

1. INTRODUCTION Integrated optical devices such as surface emitting laser array, photo detector array and OEICs promise high performance parallel processing. Although these devices have two-dimensional paral-lelism for pattern information processing, their potential capabilities are not utilized in conventional parallel processing systems. The " I/O bottleneck " between processing element (PE) array and I/O devices sets the limit to the processing speed. In order to overcome the I/O bottleneck, two-dimensional interconnections between them are required. The interconnections, however, can not be implemented by using conventional macro-scale wiring technology even if the integrated optical devices are used. Only the integrated wiring technology that is VLSI technology can implement the interconnections. It means that the processing element should be so compact to be implemented with integrated optical devices. Integrated PE and optical device array realizes fully parallel processing with high computing performance. In this paper, architectures of compact PE array and experimental systems, some experimental results on the system performance for applications, and a design of an integrated one chip parallel processing system are shown.